1. Field of the Invention
The present invention relates to an interconnection structure suitably applicable to a semiconductor device and a method of forming the same.
2. Description of the Related Art
As a conventional interconnection formation technique for semiconductor integrated circuits, a technique of forming a metal film represented by an aluminum (Al) film or an Al alloy film by sputtering is generally extensively used.
However, to meet the recent demands for further downsized and integrated semiconductor devices, micropatterned interconnections and multilayer interconnections are acceleratedly advanced. In a logic device having this multilayer interconnection, a wiring delay is becoming a dominant cause of a device signal delay. A signal delay of a device is proportional to the product of a wiring resistance and a wiring capacitance. Accordingly, to improve the wiring delay, it is important to reduce the wiring resistance and the wiring capacitance. To this end, it is presently necessary to select suitable interconnection materials and contact hole burying materials and develop a technique which forms interconnections by using the selected materials without causing any inconveniences in fabrication.